用Verilog设计通用二进制encoder

`timescale 1ns / 100ps


module encoder_generic(A, EN, Y);
    parameter N, S;
    input [N-1:0] A;
    input EN;
    output reg [S-1:0] Y;
    integer i,on;

    always @ (*) begin
        Y = 0;
        if (EN) begin
            on = 0;
            for (i=0; i<N; i=i+1)
                if (A[i]==1) begin
                    Y = i;
                    on = on + 1;
                end
            if (on != 1) Y = 0;
        end
    end
endmodule


module test_encoder_generic();
    parameter S=4, N=2**S;
    reg [N-1:0] A;
    reg EN;
    wire [S-1:0] Y;
    integer i,j,k;

    encoder_generic #(N,S) UUT(A, EN, Y);
    initial begin
        for (i=0; i<2; i=i+1)
            for (j=0; j<N; j=j+1) begin
                EN = i;
                A = 0; A[j] = 1;
                #10;
                if ((EN==0) && (Y!=0))
                    $display("Y should be zero when EN=0!");
                if ((EN==1) && (Y!=j))
                    $display("Error j=%d",j);
            end
        $display("Test Done!");
    end
endmodule